Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.11889/4428
Title: Bit-swapping LFSR and scan-chain ordering : a novel technique for peak- and average-power reduction in scan-based BIST
Authors: Abu Issa, Abdallatif
Quigley, Steven F.
Keywords: Integrated circuits - Large scale integration
Linear operators
Issue Date: 2009
Abstract: This paper presents a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2×1 multiplexer. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patternsproduced by a conventional LFSR. Hence, it reduces the overall switchingactivity in the circuit under test during test applications. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycle or while scanning out a response to a signature analyzer. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results on ISCAS’89 benchmark circuits show up to 65% and 55% reductions in average and peak power, respectively.
Description: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009, pp. 755-759
URI: http://hdl.handle.net/20.500.11889/4428
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