Please use this identifier to cite or link to this item:
http://hdl.handle.net/20.500.11889/4428
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Abu Issa, Abdallatif | |
dc.contributor.author | Quigley, Steven F. | |
dc.date.accessioned | 2017-03-07T10:13:56Z | |
dc.date.available | 2017-03-07T10:13:56Z | |
dc.date.issued | 2009 | |
dc.identifier.uri | http://hdl.handle.net/20.500.11889/4428 | |
dc.description | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009, pp. 755-759 | en_US |
dc.description.abstract | This paper presents a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2×1 multiplexer. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patternsproduced by a conventional LFSR. Hence, it reduces the overall switchingactivity in the circuit under test during test applications. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycle or while scanning out a response to a signature analyzer. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results on ISCAS’89 benchmark circuits show up to 65% and 55% reductions in average and peak power, respectively. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Integrated circuits - Large scale integration | en_US |
dc.subject | Linear operators | en_US |
dc.subject.lcsh | Integrated Circuits - Computer-aided design | |
dc.subject.lcsh | Shift operators (Operator theory) | |
dc.subject.lcsh | Integrated circuits - Design and construction | |
dc.title | Bit-swapping LFSR and scan-chain ordering : a novel technique for peak- and average-power reduction in scan-based BIST | en_US |
dc.type | Article | en_US |
newfileds.department | Graduate Studies | en_US |
newfileds.item-access-type | open_access | en_US |
newfileds.thesis-prog | none | en_US |
newfileds.general-subject | none | en_US |
item.languageiso639-1 | other | - |
item.fulltext | With Fulltext | - |
item.grantfulltext | open | - |
Appears in Collections: | Fulltext Publications |
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04838831_002.pdf | 229.13 kB | Adobe PDF | View/Open |
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