Optimized large-capacity content addressable memory (CAM) for mobile devices

Abstract

A content addressable memory system includes CAM cells, each having a compare circuit and a memory bit cell that stores complementary bits. The main CAM design challenge is to reduce power consumption associated with large amount of parallel switching circuitry, without sacrificing speed or density. In this paper, we present a new technique to eliminate crowbar current during bit-cell write operation (saving 0.0114mA per cell in 22nm process), reduce average current consumption during cam operation and eliminate the need for routing the complementary data to every cam cell, saving routing track in smaller node technology where wire cap is dominant.