Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.11889/4366
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dc.contributor.authorMohammad, Khader-
dc.contributor.authorDodin, Ayman-
dc.contributor.authorLiu, Bao-
dc.contributor.authorAgaian, Sos-
dc.date.accessioned2017-03-04T06:40:54Z-
dc.date.available2017-03-04T06:40:54Z-
dc.date.issued2009-
dc.identifier.urihttp://hdl.handle.net/20.500.11889/4366-
dc.description.abstractWe propose a novel circuit technique to generate a reduced voltage swing (RVS) signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV) devices and the programmability of the low voltage valueen_US
dc.language.isoen_USen_US
dc.subjectIntegrated circuits - Very large scale integration - Design and constructionen_US
dc.subjectTiming circuits - Design and constructionen_US
dc.subjectVoltage regulatorsen_US
dc.titleReduced voltage scaling in clock distribution networksen_US
dc.typeArticleen_US
newfileds.departmentEngineering and TechnologyEngineering and Technologyen_US
newfileds.item-access-typeopen_accessen_US
newfileds.thesis-prognoneen_US
newfileds.general-subjectnoneen_US
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