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|Title:||Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits||Authors:||Abu Issa, Abdallatif||Keywords:||Integrated circuits - Very large scale integration - Design and construction - Data processing;Integrated circuits - Very large scale integration - Testing - Data processing;Digital integrated circuits - Testing - Data processing;Semiconductors - Design and construction||Issue Date:||2009||Abstract:||Testing of digital VLSI circuits entails m VLSI CIRCUITS any challenges as a consequence of rapid emiconductor manufacturing technology and the unprecedented levels of BIST. The results obtained while scanning in reduction in average power consumption. The BS-LFSR is to reduce peak power in scan-based BIST is presented. Finally, a technique that aims to significantly increase the fault coverage in test-peran BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques. growth of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power dissipation and test application time within acceptable limits. This dissertation proposes techniques to addresses these challenges during test. The first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the circuit-under-test (CUT). The obtained results show up to 28% power reduction for the proposed design, and up-to 63% when it is combined with another established technique. The proposed BS-LFSR is then extended for use in test-per-scan test vectors show up to 60% is then extended further to act as a multi-degree smoother for test patterns generated by conventional LFSRs before applying them to the CUT. Experimental results show up to 55% reduction in average power. Another technique that aim The new technique uses a two-phase scan-chain ordering algorithm to reduce average and peak power in scan and capture cycles. Experimental results show up to 65% and 55% reduction in average and peak power, respectively. Finally, a technique that aims to significantly increase the fault coverage in test-perscan BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques||URI:||http://hdl.handle.net/20.500.11889/4376|
|Appears in Collections:||Fulltext Publications|
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