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|Title:||Energy efficient swing signal generation circuits for clock distribution networks||Authors:||Mohammad, Khader
|Keywords:||Electric power system stability;Electric power systems - Control;Timing circuits - Design and construction;Integrated circuits - Very large scale integration - Design and construction||Issue Date:||2009||Abstract:||We propose Reduced Voltage Swing (RVS) signaling (by elevating the logic 0 voltage) as opposed to Low Voltage Swing (LVS) signaling (which reduces the logic 1 voltage). We propose an inverter which generates RVS signals, and an extension with programmable logic for adjusted logic 0 voltage. The proposed RVS scheme achieves reduced active power consumption, minimum performance degradation and minimum area overhead (without extra power supply network and a minimum number of extra transistors). Application of multi-threshold voltage design further alleviates compromises on noise margin and leakage. Experimental results based on SPICE simulation show that RVS clocking achieves an average of 37% active power consumption reduction, 8% performance degradation||URI:||http://hdl.handle.net/20.500.11889/4367|
|Appears in Collections:||Fulltext Publications|
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